 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| motorola semiconductor technical data dsp56004 dsp56004rom o r d er thi s d ocumen t b y: dsp56004/d, rev. 3 ?1996, 1997 motorola, inc. symphony ? audio dsp family 24-bit digital signal processors motorola designed the symphony? family of high-performance, programmable digital signal processors (dsps) to support a variety of digital audio applications, including dolby prologic, atrac, and lucasfilm home thx processing. software for these applications is licensed by motorola for integration into products like audio/video receivers, televisions, and automotive sound systems with such user-developed features as digital equalization and sound field processing. the dsp56004 is an mpu-style general purpose dsp, composed of an efficient 24-bit digital signal processor core, program and data memories, various peripherals optimized for audio, and support circuitry. as illustrated in figure 1 , the dsp56000 core family compatible dsp is fed by program memory, two independent data rams and two data roms, a serial audio interface (sai), serial host interface (shi), external memory interface (emi), dedicated i/o lines, on-chip phase lock loop (pll), and on-chip emulation (once ? ) port. figure 1 dsp56004 block diagram y data memory* x data memory* program memory* program control unit 24-bit dsp56000 core once tm port pll clock gen. 4 9 5 29 16-bit bus 24-bit bus interrupt control 4 irqa , irqb , nmi , reset 4 3 address generation unit pab xab yab gdb pdb xdb ydb general purpose input/ output external memory interface (emi) serial audio interface (sai) serial host interface (shi) aa0248 *refer to table 1 for memory configurations. internal data bus switch program decode controller program address generator data alu 24 24 + 56 ? 56-bit mac two 56-bit accumulators f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
ii dsp56004/d, rev. 3 motorola table of contents section 1 signal/connection descriptions . . . . . . . . . . . . . . . . . . 1-1 section 2 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 section 3 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 section 4 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 section 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 for technical assistance: telephone: 1-800-521-6274 email: dsphelp@dsp.sps.mot.com internet: http://www.motorola-dsp.com data sheet conventions t his data sheet uses the following conventions: overbar used to indicate a signal that is active when pulled low (for example, the reset pin is active when low.) asserted means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol note: values for v il , v ol , v ih , and v oh are defined by individual product specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56004 features motorola dsp56004/d, rev. 3 iii features digital signal processing core ? efficient, object code compatible with the 24-bit dsp56000 core engine ? up to 40.5 million instructions per second (mips)24.7 ns instruction cycle at 81 mhz; up to 324 million operations per second (mops) at 81 mhz ? highly parallel instruction set with unique dsp addressing modes ? two 56-bit accumulators including extension byte ? parallel 24 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) ? double precision 48 48-bit multiply with 96-bit result in 6 instruction cycles ? 56-bit addition/subtraction in 1 instruction cycle ? fractional and integer arithmetic with support for multiprecision arithmetic ? hardware support for block floating-point fast fourier transforms (fft) ? hardware nested do loops ? zero-overhead fast interrupts (2 instruction cycles) ? four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories ? fabricated in high-density cmos memory ? on-chip modified harvard architecture which permits simultaneous accesses to program and two data memories ? bootstrap loading from serial host interface or external memory interface table 1 memory configuration (word width is 24 bits) part type program x data y data boot-strap rom rom ram rom ram rom ram dsp56004 1 none 512 256 256 256 256 64 dsp56004rom 2 2560 256 256 256 256 256 64 note: 1. x data rom is programmed with log 2 x and 2 x tables ; y data rom is programmed with a sine table. 2. these roms may be factory programmed with data/program provided by the application developer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . iv dsp56004/d, rev. 3 motorola dsp56004 features peripheral and support circuits ? serial audio interface (sai) includes two receivers and three transmitters, master or slave capability, implementation of i 2 s, sony, and matsushita audio protocols; and two sets of sai interrupt vectors ? serial host interface (shi) features single master capability, 10-word receive fifo, and support for 8-, 16-, and 24-bit words ? external memory interface (emi), implemented as a peripheral supporting: C page-mode drams (one or two chips): 64 k 4, 256 k 4, and 4 m 4 bits C srams (one to four): 256 k 8 bits C data bus may be 4 or 8 bits wide C data words may be 8, 12, 16, 20, or 24 bits wide ? four dedicated, independent, programmable general purpose input/output (gpio) lines ? on-chip peripheral registers memory mapped in data memory space ? three external interrupt request pins ? on-chip emulation (once) port for unobtrusive, processor speed- independent debugging ? software-programmable, phase lock loop-based (pll) frequency synthesizer for the core clock ? power-saving wait and stop modes ? fully static, hcmos design for operating frequencies down to dc ? 80-pin plastic quad flat pack surface-mount package; 14 14 2.20 mm (2.15C2.45 mm range); 0.65 mm lead pitch ? complete pinout compatibility between dsp56004, dsp56004rom, dsp56007, and dsp56009 for easy upgrades ? 5 v power supply f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dsp56004 product documentation motorola dsp56004/d, rev. 3 v product documentation table 2 lists the documents that provide a complete description of the dsp56004 and are required to design properly with the part. documentation is available from a local motorola distributor, a motorola semiconductor sales office, a motorola literature distribution center, or through the motorola dsp home page on the internet (the source for the latest information). table 2 dsp56004 documentation document name description of content order number dsp56000 family manual dsp56000 core family architecture and the 24-bit core processor and instruction set dsp56kfamum/ad dsp56004 users manual memory, peripherals, and interfaces dsp56004um/ad dsp56004 technical data electrical and timing specifications, and pin and package descriptions dsp56004/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . vi dsp56004/d, rev. 3 motorola dsp56004 product documentation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004/d, rev. 3 1-1 section 1 signal/connection descriptions signal groupings the dsp56004 input and output signals are organized into the nine functional groups, as shown in table 1-1 . the individual signals are illustrated in figure 1-1 . table 1-1 dsp56004 functional group signal allocations functional group number of signals detailed description power (v cc )9 table 1-2 ground (gnd) 13 table 1-3 phase lock loop (pll) 3 table 1-4 external memory interface (emi) 29 table 1-5 and table 1-6 interrupt and mode control 4 table 1-7 serial host interface (shi) 5 table 1-8 serial audio interface (sai) 9 table 1-9 and table 1-10 general purpose input/output (gpio) 4 table 1-11 on-chip emulation (once) port 4 table 1-12 total 80 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-2 dsp56004/d, rev. 3 motorola signal/connection descriptions signal groupings figure 1-1 dsp56004 signals ma0Cma14 md0Cmd7 mwr ma17/mcs1 /mras ma16/mcs2 /mcas gnd q v ccq reset moda/irqa modb/irqb modc/nmi ss /ha2 miso/sda sck/scl gnd s v ccs wsr sckr sdi0 dsck/os1 dsi/os0 dso dr once? port c port b port a external memory mode/interrupt 80 signals serial host rec0 sdo1 tran1 wst sckt sdo0 tran0 interface mrd mcs0 serial audio interface interface mosi/ha0 sdo2 tran2 sdi1 rec1 gpio0Cgpio3 gpio hreq v ccp gnd p pcap pll pinit ma15/mcs3 extal gnd a v cca gnd d v ccd reset aa0249g port power inputs ground control 2 2 3 3 4 2 3 8 4 15 dsp56007 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions power motorola dsp56004/d, rev. 3 1-3 power ground table 1-2 power inputs power name description v ccp pll power v ccp provides isolated power for the phase lock loop (pll). the voltage should be well-regulated and the input should be provided with an extremely low impedance path to the v cc power rail. v ccq quiet power v ccq provides isolated power for the internal processing logic. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v cca address bus power v cca provides isolated power for sections of the address bus i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v ccd data bus power v ccd provides isolated power for sections of the data bus i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v ccs serial interface power v ccs provides isolated power for the shi and sai. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. table 1-3 grounds ground name description gnd p pll ground gnd p is ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.47 m f capacitor located as close as possible to the chip package. gnd q quiet ground gnd q provides isolated ground for the internal processing logic. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd a address bus ground gnd a provides isolated ground for sections of the address bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd d data bus ground gnd d provides isolated ground for sections of the data bus i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd s serial interface ground gnd s provides isolated ground for the shi and sai. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-4 dsp56004/d, rev. 3 motorola signal/connection descriptions clock and pll signals clock and pll signals note: while the pll on this dsp is identical to the pll described in the dsp56000 family manual , two of the signals have not been implemented externally. specifically, there is no plock signal or ckout signal available. therefore, the internal clock is not directly accessible and there is no external indication that the pll is locked. these signals were omitted to reduce the number of pins and allow this dsp to be put in a smaller, less expensive package. table 1-4 clock and pll signals signal name signal type state during reset signal description extal input input external clock/crystal this input should be connected to an external clock source. if the pll is enabled, this signal is internally connected to the on-chip pll. the pll can multiply the frequency on the extal pin to generate the internal dsp clock. the pll output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two pll output clock periods. if the pll is disabled, extal is divided by two to produce the four-phase instruction cycle clock. pcap input input pll filter capacitor this input is used to connect a high- quality (high q factor) external capacitor needed for the pll filter. the capacitor should be as close as possible to the dsp with heavy, short traces connecting one terminal of the capacitor to pcap and the other terminal to v ccp . the required capacitor value is specified in table 2-6 on page 2-6. note: when short lock time is critical, low dielectric absorption capacitors such as polystyrene, polypropylene, or teflon are recommended. if the pll is not used (i.e., it remains disabled at all times), there is no need to connect a capacitor to the pcap pin. it may remain unconnected, or be tied to either v cc or gnd. pinit input input pll initialization (pinit) during the assertion of hardware reset, the value on the pinit line is written into the pen bit of the pctl register. when set, the pen bit enables the pll by causing it to derive the internal clocks from the pll voltage controlled oscillator output. when the bit is cleared, the pll is disabled and the dsps internal clocks are derived from the clock connected to the extal signal. after hardware reset is deasserted, the pinit signal is ignored. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions external memory interface (emi) motorola dsp56004/d, rev. 3 1-5 external memory interface (emi) table 1-5 external memory interface (emi) signals signal name signal type state during reset signal description ma0Cma14 output table 1-6 memory address lines 0C14 the ma0Cma10 lines provide the multiplexed row/column addresses for dram accesses. lines ma0Cma14 provide the non-multiplexed address lines 0C14 for sram accesses. ma15 mcs3 output table 1-6 memory address line 15 (ma15) this line functions as the non-multiplexed address line 15. memory chip select 3 (mcs3 ) for sram accesses, this line functions as memory chip select 3. ma16 mcs2 mcas output table 1-6 memory address line 16 (ma16) this line functions as the non-multiplexed address line 16 or as memory chip select 2 for sram accesses. memory chip select 2 (mcs2 ) for sram access, this line functions as memory chip select 2. memory column address strobe (mcas ) this line functions as the memory column address strobe (mcas ) during dram accesses. ma17 mcs1 mras output table 1-6 memory address line 17 (ma17) this line functions as the non-multiplexed address line 17. memory chip select 1 (mcs1) this line functions as chip select 1 for sram accesses. memory row address strobe (mras ) this line also functions as the memory row address strobe during dram accesses. mcs0 output table 1-6 memory chip select 0 this line functions as memory chip select 0 for sram accesses. mwr output table 1-6 memory write strobe this line is asserted when writing to external memory. mrd output table 1-6 memory read strobe this line is asserted when reading external memory. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-6 dsp56004/d, rev. 3 motorola signal/connection descriptions external memory interface (emi) . md0Cmd7 bidi- rectional tri-stated data bus these signals provide the bidirectional data bus for emi accesses. they are inputs during reads from external memory, outputs during writes to external memory, and tri- stated if no external access is taking place. if the data bus width is defined as four bits wide, only signals md0Cmd3 are active, while signals md4Cmd7 remain tri-stated. while tri-stated, md0Cmd7 are disconnected from the pins and do not require external pull-ups. table 1-6 emi states during reset and stop states signal operating mode hardware reset software reset individual reset stop mode ma0Cma14 driven high previous state previous state previous state ma15 mcs3 driven high driven high driven high driven high previous state driven high previous state driven high ma16 mcs2 mcas: dram refresh disabled dram refresh enabled driven high driven high driven high driven high driven high driven high driven high driven high previous state driven high driven high driven low previous state driven high driven high driven high ma17 mcs1 mras : dram refresh disabled dram refresh enabled driven high driven high driven high driven high driven high driven high driven high driven high previous state driven high driven high driven low previous state driven high driven high driven high mcs0 driven high driven high driven high driven high mwr driven high driven high driven high driven high mrd driven high driven high driven high driven high table 1-5 external memory interface (emi) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions interrupt and mode control motorola dsp56004/d, rev. 3 1-7 interrupt and mode control the interrupt and mode control signals select the dsps operating mode as it comes out of hardware reset and receives interrupt requests from external sources after reset. table 1-7 interrupt and mode control signals signal name signal type state during reset signal description moda irqa input input (moda) mode select a this input signal has three functions: ? to work with the modb and modc signals to select the dsps initial operating mode, ? to allow an external device to request a dsp interrupt after internal synchronization, and ? to turn on the internal clock generator when the dsp is in the stop processing state, causing the dsp to resume processing. moda is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the moda signal changes to the external interrupt request irqa . the dsp operating mode can be changed by software after reset. external interrupt request a (irqa ) the irqa input is a synchronized external interrupt request. it may be programmed to be level-sensitive or negative-edge- triggered. when the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqa will generate multiple interrupts also increases. while the dsp is in the stop mode, asserting irqa gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. hardware reset causes this input to function as moda. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-8 dsp56004/d, rev. 3 motorola signal/connection descriptions interrupt and mode control modb irqb input input (modb) mode select b this input signal has two functions: ? to work with the moda and modc signals to select the dsps initial operating mode, and ? to allow an external device to request a dsp interrupt after internal synchronization. modb is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the modb signal changes to the external interrupt request irqb . the dsp operating mode can be changed by software after reset. external interrupt request b (irqb )the irqb input is a synchronized external interrupt request. it may be programmed to be level-sensitive or negative-edge- triggered. when the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqb will generate multiple interrupts also increases. hardware reset causes this input to function as modb. table 1-7 interrupt and mode control signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions interrupt and mode control motorola dsp56004/d, rev. 3 1-9 modc nmi input, edge- triggered input (modc) mode select c this input signal has two functions: ? to work with the moda and modb signals to select the dsps initial operating mode, and ? to allow an external device to request a dsp interrupt after internal synchronization. modc is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the modc signal changes to the non-maskable interrupt request, nmi . the dsp operating mode can be changed by software after reset. non-maskable interrupt request the nmi input is a negative-edge-triggered external interrupt request. this is a level 3 interrupt that can not be masked out. triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on nmi will generate multiple interrupts also increases. hardware reset causes this input to function as modc. reset input active reset this input causes a direct hardware reset of the processor. when reset is asserted, the dsp is initialized and placed in the reset state. a schmitt-trigger input is used for noise immunity. when the reset signal is deasserted, the initial dsp operating mode is latched from the moda, modb, and modc signals. the dsp also samples the pinit signal and writes its status into the pen bit of the pll control register. when the dsp comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the reset signal. however, the probability that noise on reset will generate multiple resets increases with increasing rise time of the reset signal. for proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware reset state. table 1-7 interrupt and mode control signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-10 dsp56004/d, rev. 3 motorola signal/connection descriptions serial host interface (shi) serial host interface (shi) the serial host interface (shi) has five i/o signals, which may be configured to operate in either spi or i 2 c mode. table 1-8 lists the shi signals. table 1-8 serial host interface (shi) signals signal name signal type state during reset signal description sck scl input or output input or output tri-stated spi serial clock (sck) the sck signal is an output when the spi is configured as a master, and a schmitt- trigger input when the spi is configured as a slave. when the spi is configured as a master, the sck signal is derived from the internal shi clock generator. when the spi is configured as a slave, the sck signal is an input, and the clock signal from the external master synchronizes the data transfer. the sck signal is ignored by the spi if it is defined as a slave and the slave select (ss ) signal is not asserted. in both the master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi transfer protocol. i 2 c serial clock (scl) scl carries the clock for bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. scl should be connected to v cc through a pull-up resistor. the maximum allowed internally generated bit clock frequency is f osc / 4 for the spi mode and f osc / 6 for the i 2 c mode where f osc is the clock on extal. the maximum allowed externally generated bit clock frequency is f osc / 3 for the spi mode and f osc / 5 for the i 2 c mode. this signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions serial host interface (shi) motorola dsp56004/d, rev. 3 1-11 miso sda input or output input or output tri-stated spi master-in-slave-out (miso) when the spi is configured as a master, miso is the master data input line. the miso signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when configured for the spi slave mode, and tri-stated if configured for the spi slave mode when ss is deasserted. i 2 c serial data and acknowledge (sda) in i 2 c mode, sda is a schmitt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v cc through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is high in the case of start and stop events. a high-to-low transition of the sda line while scl is high is an unique situation, and is defined as the start event. a low-to-high transition of sda while scl is high is an unique situation, and is defined as the stop event. note: this line is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). mosi ha0 input or output input tri-stated spi master-out-slave-in (mosi) when the spi is configured as a master, mosi is the master data output line. the mosi signal is used in conjunction with the miso signal for transmitting and receiving serial data. mosi is the slave data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode. i 2 c slave address 0 (ha0) this signal uses a schmitt- trigger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when the shi is configured for the i 2 c master mode. note: this signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). table 1-8 serial host interface (shi) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-12 dsp56004/d, rev. 3 motorola signal/connection descriptions serial host interface (shi) ss ha2 input input tri-stated spi slave select (ss ) this signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for transfer. when configured for the spi master mode, this signal should be kept deasserted. if it is asserted while configured as spi master, a bus error condition will be flagged. i 2 c slave address 2 (ha2) this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. if ss is deasserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. note: this signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). hreq input or output tri-stated host request this signal is an active low schmitt- trigger input when configured for the master mode, but an active low output when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input and when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing the data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. note: this signal is tri-stated during hardware, software, individual reset, or when the hreq[1:0] bits (in the hcsr) are cleared (no need for external pull-up in this state). table 1-8 serial host interface (shi) signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions serial audio interface (sai) motorola dsp56004/d, rev. 3 1-13 serial audio interface (sai) the sai is composed of separate receiver and transmitter sections. sai receiver section table 1-9 serial audio interface (sai) receiver signals signal name signal type state during reset signal description sdi0 input tri-stated serial data input 0 while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. sdi0 is the serial data input for receiver 0. note: this signal is high impedance during hardware or software reset, while receiver 0 is disabled (r0en = 0), or while the dsp is in the stop state. sdi1 input tri-stated serial data input 1 while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. sdi1 is the serial data input for receiver 1. note: this signal is high impedance during hardware or software reset, while receiver 1 is disabled (r1en = 0), or while the dsp is in the stop state. sckr input or output tri-stated receive serial clock sckr is an output if the receiver section is programmed as a master, and a schmitt-trigger input if programmed as a slave. while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. note: sckr is high impedance if all receivers are disabled (individual reset) and during hardware or software reset, or while the dsp is in the stop state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-14 dsp56004/d, rev. 3 motorola signal/connection descriptions serial audio interface (sai) wsr input or output tri-stated word select receive (wsr) wsr is an output if the receiver section is configured as a master, and a schmitt-trigger input if configured as a slave. wsr is used to synchronize the data word and to select the left/right portion of the data sample. note: wsr is high impedance if all receivers are disabled (individual reset), during hardware reset, during software reset, or while the dsp is in the stop state. while in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary. table 1-9 serial audio interface (sai) receiver signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions serial audio interface (sai) motorola dsp56004/d, rev. 3 1-15 sai transmitter section table 1-10 serial audio interface (sai) transmitter signals signal name signal type state during reset signal description sdo0 output driven high serial data output 0 (sdo0) sdo0 is the serial output for transmitter 0. sdo0 is driven high if transmitter 0 is disabled, during individual reset, hardware reset, and software reset, or when the dsp is in the stop state. sdo1 output driven high serial data output 1 (sdo1) sdo1 is the serial output for transmitter 1. sdo1 is driven high if transmitter 1 is disabled, during individual reset, hardware reset and software reset, or when the dsp is in the stop state. sdo2 output driven high serial data output 2 (sdo2) sdo2 is the serial output for transmitter 2. sdo2 is driven high if transmitter 2 is disabled, during individual reset, hardware reset and software reset, or when the dsp is in the stop state. sckt input or output tri-stated serial clock transmit (sckt) this signal provides the clock for the sai. sckt can be an output if the transmit section is configured as a master, or a schmitt-trigger input if the transmit section is configured as a slave. when the sckt is an output, it provides an internally generated sai transmit clock to external circuitry. when the sckt is an input, it allows external circuitry to clock data out of the sai. note: sckt is high impedance if all transmitters are disabled (individual reset), during hardware reset, software reset, or while the dsp is in the stop state. while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. wst input or output tri-stated word select transmit (wst) wst is an output if the transmit section is programmed as a master, and a schmitt- trigger input if it is programmed as a slave. wst is used to synchronize the data word and select the left/right portion of the data sample. note: wst is high impedance if all transmitters are disabled (individual reset), during hardware or software reset, or while the dsp is in the stop state. while in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-16 dsp56004/d, rev. 3 motorola signal/connection descriptions general purpose i/o general purpose i/o on-chip emulation (once tm ) port there are four signals associated with the once port controller and its serial interface. table 1-11 general purpose i/o (gpio) signals signal name signal type state during reset signal description gpio0C gpio3 standard output, open-drain output, or input disconnected gpio lines can be used for control and handshake functions between the dsp and external circuitry. each gpio line can be configured individually as disconnected, open-drain output, standard output, or an input. note: hardware reset or software reset configures all the gpio lines as disconnected (external circuitry connected to these pins may need pull- ups until the pins are configured for operation). table 1-12 on-chip emulation port signals signal name signal type state during reset signal description dsi os0 input output output, driven low debug serial input (dsi) the dsi signal is the signal through which serial data or commands are provided to the once port controller. the data received on the dsi signal will be recognized only when the dsp has entered the debug mode of operation. data must have valid ttl logic levels before the serial clock falling edge. data is al ways shifted into the once port most significant bit (msb) first. operating status 0 (os0) when the dsp is not in the debug mode, the os0 signal provides information about the dsp status if it is an output and used in conjunction with the os1 signal. when switching from output to input, the signal is tri-stated. note: if the once port is in use, an external pull-down resistor should be attached to the dsi/os0 signal. if the once port is not in use, the resistor is not required. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . signal/connection descriptions on-chip emulation (once tm ) port motorola dsp56004/d, rev. 3 1-17 dsck os1 input output output, driven low debug serial clock (dsck) the dsck/os1 signal, when an input, is the signal through which the serial clock is supplied to the once port. the serial clock provides pulses required to shift data into and out of the once port. data is clocked into the once port on the falling edge and is clocked out of the once port on the rising edge. operating status 1 (os1) if the os1 signal is an output and used in conjunction with the os0 signal, it provides information about the dsp status when the dsp is not in the debug mode. the debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. the signal is tri-stated when it is changing from input to output. note: if the once port is in use, an external pull-down resistor should be attached to the dsck/os1 pin. if the once port is not in use, the resistor is not required. dso output driven high debug serial output (dso) the dso line provides the data contained in one of the once port controller registers as specified by the last command received from the command controller. the most significant bit (msb) of the data word is always shifted out of the once port first. data is clocked out of the once port on the rising edge of dsck. the dso line also provides acknowledge pulses to the external command controller. when the dsp enters the debug mode, the dso line will be pulsed low to indicate that the once port is waiting for commands. after receiving a read command, the dso line will be pulsed low to indicate that the requested data is available and the once port is ready to receive clock pulses in order to deliver the data. after receiving a write command, the dso line will be pulsed low to indicate that the once port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. note: during hardware reset and when idle, the dso line is held high. table 1-12 on-chip emulation port signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 1-18 dsp56004/d, rev. 3 motorola signal/connection descriptions on-chip emulation (once tm ) port dr input input debug request (dr ) the debug request input provides a means of entering the debug mode of operation. this signal, when asserted (pulled low), will cause the dsp to finish the current instruction being executed, to save the instruction pipeline information, to enter the debug mode, and to wait for commands to be entered from the debug serial input line. while the dsp is in the debug mode, the user can reset the once port controller by asserting dr , waiting for an acknowledge pulse on dso, and then deasserting dr . it may be necessary to reset the once port controller in cases where synchronization between the once port controller and external circuitry is lost. asserting dr when the dsp is in the wait or the stop mode, and keeping it asserted until an acknowledge pulse in the dsp is produced, puts the dsp into the debug mode. after receiving the acknowledge pulse, dr must be deasserted before sending the first once port command. for more information, see methods of entering the debug mode in the dsp56000 family manual . note: if the once port is not in use, an external pull-up resistor should be attached to the dr line. table 1-12 on-chip emulation port signals (continued) signal name signal type state during reset signal description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004/d, rev. 3 2-1 section 2 specifications introduction the dsp56004 is fabricated in high density cmos with transistor-transistor logic (ttl) compatible inputs and outputs. maximum ratings note: in the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite direction. therefore, a maximum value for a specification will never occur in the same device that has a minimum value for another specification; adding a maximum to a minimum represents a condition that can never exist. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-2 dsp56004/d, rev. 3 motorola specifications thermal characteristics thermal characteristics table 2-1 maximum ratings (gnd = 0 v dc ) rating symbol value unit supply voltage v cc C0.3 to +7.0 v all input voltages: ? 50 and 66 mhz ? 81 mhz v in (gnd C 0.5) to (v cc + 0.5) (gnd C 0.25) to (v cc + 0.25) v current drain per pin excluding v cc and gnd i 10 ma operating temperature range: ? 50 and 66 mhz ? 81 mhz t j C40 to +125 C40 to +120 c c storage temperature t stg C55 to +125 c table 2-2 thermal characteristics characteristic symbol qfp value 3 qfp value 4 unit junction-to-ambient thermal resistance 1 r q ja or q ja 70.4 45.1 ? c/w junction-to-case thermal resistance 2 r q jc or q jc 16.4 ? c/w thermal characterization parameter y jt 3.2 ? c/w notes: 1. junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided printed circuit board per semi g38-87 in natural convection.(semi is semiconductor equipment and materials international, 805 east middlefield rd., mountain view, ca 94043, (415) 964-5111) 2. junction-to-case thermal resistance is based on measurements using a cold plate per semi g30- 88, with the exception that the cold plate temperature is used for the case temperature. 3. these are measured values. see note 1 for test board conditions. 4. these are measured values; testing is not complete. values were measured on a non-standard four-layer thermal test board (two internal planes) at one watt in a horizontal configuration. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications dc electrical characteristics motorola dsp56004/d, rev. 3 2-3 dc electrical characteristics table 2-3 dc electrical characteristics characteristics symbol 50 mhz 66 mhz 81 mhz unit min typ max min typ max min typ max supply voltage v cc 4.5 5.0 5.5 4.5 5.0 5.5 4.75 5.0 5.25 v input high voltage ? extal ? reset ? moda, modb, modc ? shi inputs 1 ? all other inputs v ihc v ihr v ihm v ihs v ih 4.0 2.5 3.5 0.7 v cc 2.0 v cc v cc v cc v cc v cc 4.0 2.5 3.5 0.7 v cc 2.0 v cc v cc v cc v cc v cc 4.0 2.5 3.5 0.7 v cc 2.0 v cc v cc v cc v cc v cc v v v v v input low voltage ? extal ? moda, modb, modc ? shi inputs 1 ? all other inputs v ilc v ilm v ils v il C0.5 C0.5 C0.5 C0.5 0.6 2.0 0.3 v cc 0.8 C0.5 C0.5 C0.5 C0.5 0.6 2.0 0.3 v cc 0.8 C0.25 C0.25 C0.25 C0.25 0.6 2.0 0.3 v cc 0.8 v v v v input leakage current ? extal, reset , moda, modb, modc, dr ? other input pins (@ 2.4 v/0.4 v) i in C1 C10 1 10 C1 C10 1 10 C1 C10 1 10 m a m a high impedance (off-state) input current (@ 2.4 v / 0.4 v) i tsi C10 10 C10 10 C10 10 m a output high voltage (i oh = C0.4 ma) v oh 2.4 2.4 2.4 v output low voltage (i ol = 3.2 ma) sck/scl i ol = 6.7 ma miso/sda i ol = 6.7 ma hreq i ol = 6.7 ma v ol 0.4 0.4 0.4 v internal supply current ? normal mode ? wait mode ? stop mode 2 i cci i ccw i ccs 75 14 5 105 4 25 110 103 18 5 130 4 30 110 120 20 5 155 4 30 110 ma ma m a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-4 dsp56004/d, rev. 3 motorola specifications ac electrical characteristics ac electrical characteristics the timing waveforms in the ac electrical characteristics are tested with a v il maximum of 0.5 v and a v ih minimum of 2.4 v for all pins, except extal, reset , moda, modb, modc, and shi pins (mosi/ha0, ss /ha2, miso/sda, sck/ scl, hreq ). these pins are tested using the input levels set forth in the dc electrical characteristics. ac timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signals transition. dsp56004 output levels are measured with the production test machine v ol and v oh reference levels set at 0.8 v and 2.0 v, respectively. all output delays are given for a 50 pf load unless otherwise specified. for load capacitance greater than 50 pf, the drive capability of the output pins typically decreases linearly: 1. at 1.5 ns per 10 pf of additional capacitance at all output pins except mosi/ ha0, miso/sda, sck/scl, hreq 2. at 1.0 ns per 10 pf of additional capacitance at output pins mosi/ha0, miso/sda, sck/scl, hreq (in spi mode only) pll supply current 0.7 1.1 1.0 1.5 1.2 2.0 ma input capacitance 3 c in 101010pf notes: 1. the shi inputs are: mosi/ha0, ss /ha2, miso/sda, sck/scl, and hreq . 2. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). pll signals are disabled during stop state. 3. periodically sampled and not 100% tested 4. maximum values are derived using the methodology described in section 4 . actual maximums are application dependent and may vary widely from these numbers. table 2-3 dc electrical characteristics characteristics symbol 50 mhz 66 mhz 81 mhz unit min typ max min typ max min typ max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications internal clocks motorola dsp56004/d, rev. 3 2-5 internal clocks for each occurrence of t h , t l , t c or i cyc , substitute with the numbers in table 2-4 . external clock (extal pin) the dsp56004 system clock is externally supplied via the extal pin. timings shown in this document are valid for clock rise and fall times of 3 ns maximum. table 2-4 internal clocks characteristics symbol expression minimum maximum internal operation frequency f internal clock high period ? with pll disabled ? with pll enabled and mf 4 ? with pll enabled and mf > 4 t h et h 0.48 t c 0.467 t c 0.52 t c 0.533 t c internal clock low period ? with pll disabled ? with pll enabled and mf 4 ? with pll enabled and mf > 4 t l et l 0.48 t c 0.467 t c 0.52 t c 0.533 t c internal clock cycle time t c (df /mf) et c instruction cycle time i cyc 2 t c table 2-5 external clock (extal pin) no. characteristics sym. 50 mhz 66 mhz 81 mhz unit min max min max min max frequency of external clock (extal pin) ef 0 50 0 66 0 81 mhz 1 external clock input highextal pin 1 ? with pll disabled (46.7%C53.3% duty cycle) ? with pll enabled (42.5%C57.5% duty cycle) et h 9.3 8.5 235500 7.1 6.4 235500 5.8 5.2 235500 ns ns 2 external clock input lowextal pin 1 ? with pll disabled (46.7%C53.3% duty cycle) ? with pll enabled (42.5%C57.5% duty cycle) et l 9.3 8.5 235500 7.1 6.4 235500 5.8 5.2 235500 ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-6 dsp56004/d, rev. 3 motorola specifications phase lock loop (pll) characteristics phase lock loop (pll) characteristics 3 external clock cycle time 1 ? with pll disabled ? with pll enabled et c 20 20 409600 15.15 15.15 409600 12.3 12.3 409600 ns ns 4 instruction cycle time = i cyc = 2 t c 1 ? with pll disabled ? with pll enabled i cyc 40 40 819200 30.3 30.3 819200 24.7 24.7 819200 ns ns note: 1. external clock input high and external clock input low are measured at 50% of the input transition. figure 2-1 external clock timing table 2-6 phase lock loop (pll) characteristics characteristics expression min max unit vco frequency when pll enabled mf ef 10 f 1 mhz pll external capacitor (pcap pin to v ccp ) mf c pcap 1 @ mf 4 @ mf > 4 mf 340 mf 380 mf 480 mf 970 pf pf note: 1. cpcap is the value of the pll capacitor (connected between pcap pin and v ccp ) for mf = 1. the recommended value for cpcap is 400 pf for mf 4 and 540 pf for mf > 4. the maximum vco frequency is limited to the internal operation frequency, defined in table 2-4 . table 2-5 external clock (extal pin) (continued) no. characteristics sym. 50 mhz 66 mhz 81 mhz unit min max min max min max et h et l et c extal 1 2 3 4 aa0250 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications reset, stop, mode select, and interrupt timing motorola dsp56004/d, rev. 3 2-7 reset, stop, mode select, and interrupt timing table 2-7 reset, stop, mode select, and interrupt timing (c l = 50 pf + 2 ttl loads) no. characteristics all frequencies unit min max 10 minimum reset assertion width: ? pll disabled ? pll enabled 1 25 t c 2500 et c ns ns 14 mode select setup time 21 ns 15 mode select hold time 0 ns 16 minimum edge-triggered interrupt request assertion width 13 ns 16a minimum edge-triggered interrupt request deassertation width 13 ns 18 delay from irqa , irqb , nmi assertion to gpio valid caused by first interrupt instruction execution 12 t c + t h ns 22 delay from general purpose output valid to interrupt request deassertation for level sensitive fast interruptsif second interrupt instruction is: 2 ? single cycle ? two cycles t l C 31 (2 t c ) + t l C 31 ns ns 25 duration of irqa assertion for recovery from stop state 12 ns 27 duration for level sensitive irqa assertion to ensure interrupt service (when exiting stop) ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17 = 1 6 t c + t l 12 ns ns note: 1. this timing requirement is sensitive to the quality of the external pll capacitor connected to the pcap pin. for capacitor values 2 nf, asserting reset according to this timing requirement will ensure proper processor initialization for capacitors with a d c/c < 0.5%. (this is typical for ceramic capacitors.) for capacitor values > 2 nf, asserting reset according to this timing requirement will ensure proper processor initialization for capacitors with a d c/c < 0.01%. (this is typical for teflon, polystyrene, and polypropylene capacitors.) however, capacitors with values > 2 nf with a d c/c > 0.01% may require longer reset assertion to ensure proper initialization. 2. when using fast interrupts and irqa and irqb are defined as level-sensitive, then timing 22 applies to prevent multiple interrupt service. to avoid these timing restrictions, the negative edge-triggered mode is recommended when using fast interrupts. long interrupts are recommended when using level-sensitive mode. figure 2-2 reset timing reset 10 v ihr aa0251 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-8 dsp56004/d, rev. 3 motorola specifications reset, stop, mode select, and interrupt timing figure 2-3 operating mode select timing figure 2-4 external interrupt timing (negative edge-triggered) figure 2-5 external level-sensitive fast interrupt timing figure 2-6 recovery from stop state using irqa figure 2-7 recovery from stop state using irqa interrupt service v ihm v ilm v ih v il reset moda, modb modc v ihr irqa , irqb , nmi 14 15 aa0252 irqa , irqb , nmi 16 16a irqa , irqb , nmi aa0253 general purpose i/o general purpose i/o (output) irqa irqb nmi 22 18 aa0254 irqa 25 aa0255 irqa aa0256 27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications external memory interface (emi) dram timing motorola dsp56004/d, rev. 3 2-9 external memory interface (emi) dram timing (c l = 50 pf + 2 ttl loads) table 2-8 external memory interface (emi) dram timing no. characteristics symbol timing mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max 41 page mode cycle time t pc slow fast 4 t c 3 t c 80 60 61 46 49.4 37.0 ns ns 42 ras or rd assertion to data valid t rac , t ga slow fast 7 t c C 16 5 t c C 16 124 84 90 60 70.4 45.7 ns ns 43 cas assertion to data valid t cac slow fast 3 t c C 10 2 t c C 10 50 30 35 20 27.0 14.7 ns ns 44 column address valid to data valid t aa slow fast 3 t c + t l C 7 2 t c + t l C 7 63 43 46 30 36.2 23.8 ns ns 45 cas assertion to data active t clz 0 00 0 ns 46 ras assertion pulse width 1 (page mode access only) t rasp slow fast 3 t c C 11 + n 4 t c 2 t c C11 + n 3 t c 209 149 156 110 125 87.8 ns ns 47 ras assertion pulse width (single access only) t ras slow fast 7 t c C 11 5 t c C 11 129 89 95 65 75.4 50.8 ns ns 48 ras or cas deassertation to ras assertion t rp , t crp slow fast 5 t c C 5 3 t c C 5 95 55 70 40 56.7 32.0 ns ns 49 cas assertion pulse width t cas slow fast 3 t c C 10 2 t c C 10 50 30 35 20 27.0 14.7 ns ns 50 last cas assertion to ras deassertation (page mode access only) t rsh slow fast 3 t c C 15 2 t c C 15 45 25 30 15 22.0 9.7 ns ns 51 ras or wr assertion to cas deassertation t csh , t cwl slow fast 7 t c C 15 5 t c C 15 125 85 91 61 71.4 46.7 ns ns 52 ras assertion to cas assertion t rcd slow fast 4 t c C 13 3 t c C 13 67 47 47 32 36.4 24 ns ns 53 ras assertion to column address valid t rad slow fast 3 t c + t h C 13 2 t c + t h C 13 57 37 40 25 30.2 17.9 ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-10 dsp56004/d, rev. 3 motorola specifications external memory interface (emi) dram timing 54 cas deassertation pulse width (page mode access only) t cp t c C 5 15 10 7.3 ns 55 row address valid to ras assertion (row address setup time) t asr t l C 6 420.2ns 56 ras assertion to row address not valid (row address hold time) t rah slow fast 3 t c + t h C 14 2 t c + t h C 14 56 36 39 24 29.2 16.9 ns ns 57 column address valid to cas assertion (column address setup time) t asc t l C 6 420.2ns 58 cas assertion to column address not valid (column address hold time) t cah slow fast 3 t c + t h C 14 2 t c + t h C 14 56 36 39 24 29.2 16.9 ns ns 59 last cas assertion to column address not valid (column address hold time) t cah slow fast 7 t c + t h C 14 4 t c + t h C 14 136 76 100 54 78.6 41.6 ns ns 60 ras assertion to column address not valid t ar slow fast 7 t c + t h C 14 5 t c + t h C 14 136 96 100 69 78.6 53.9 ns ns 61 column address valid to ras deassertation t ral slow fast 3 t c + t l C 7 2 t c + t l C 7 63 43 46 30 36.2 23.9 ns ns 62 cas , ras , rd , or wr deassertation to wr or rd assertion t rch , t rrh slow fast 5 t c C 11 3 t c C 11 89 49 65 35 50.7 26.0 ns ns 63 cas or rd deassertation to data not valid (data hold time) t off , t gz 0 00 0 ns 64 random read or write cycle time (single access only) t rc slow fast 12 t c 8 t c 240 160 182 121 148 98.8 ns ns table 2-8 external memory interface (emi) dram timing (continued) no. characteristics symbol timing mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications external memory interface (emi) dram timing motorola dsp56004/d, rev. 3 2-11 65 wr deassertation to cas assertion t rcs slow fast 9 t c C 11 6 t c C 11 169 109 125 80 100 63.1 ns ns 66 cas assertion to wr deassertation t wch slow fast 3 t c C 13 2 t c C 13 47 27 32 17 24 11.7 ns ns 67 data valid to cas assertion (data setup time) t ds t l C 6 420.2ns 68 cas assertion to data not valid (data hold time) t dh slow fast 3 t c + t h C 14 2 t c + t h C 14 56 36 39 24 29.2 16.8 ns ns 69 ras assertion to data not valid t dhr slow fast 7 t c + t h C 14 5 t c + t h C 14 136 96 100 69 78.6 53.9 ns ns 70 wr assertion to cas assertion t wcs slow fast 4 t c C 14 3 t c C 14 66 46 47 31 35.4 23 ns ns 71 wr assertion pulse width (single cycle only) t wp slow fast 7 t c C 9 5 t c C 9 131 91 97 67 77.4 52.7 ns ns 72 ras assertion to wr deassertation (single cycle only) t wcr slow fast 7 t c C 15 5 t c C 15 125 85 91 61 71.5 46.7 ns ns 73 wr assertion to data active slow fast 3 t c + t h C 13 2 t c + t h C 13 57 37 40 25 30.2 17.9 ns ns 74 rd or wr assertion to ras deassertation (single cycle only) t roh , t rwl slow fast 7 t c C 13 5 t c C 13 127 87 93 63 73.4 48.7 ns ns note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6. table 2-8 external memory interface (emi) dram timing (continued) no. characteristics symbol timing mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-12 dsp56004/d, rev. 3 motorola specifications external memory interface (emi) dram timing figure 2-8 dram single read cycle mras mcas ma0Cma10 mwr mrd md0Cmd7 data in row address last column address 47 48 64 48 74 52 65 50 49 55 53 59 60 56 62 57 61 43 42 63 45 aa0257 44 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications external memory interface (emi) dram timing motorola dsp56004/d, rev. 3 2-13 figure 2-9 dram page mode read cycle col. address row address col. address last column address 48 46 60 50 48 65 41 54 52 54 49 49 49 61 59 58 58 53 51 55 56 57 57 57 62 43 44 44 44 43 43 data 42 63 63 63 45 45 45 in data in data in mras mcas ma0Cma10 mwr mrd md0Cmd7 aa0263 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-14 dsp56004/d, rev. 3 motorola specifications external memory interface (emi) dram timing figure 2-10 dram single write cycle 47 48 48 row address column address 64 data out 74 52 50 49 55 53 61 59 60 65 56 57 62 66 70 72 71 69 68 67 73 mras mcas ma0Cma10 mwr mrd md0Cmd7 aa0264 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications external memory interface (emi) dram timing motorola dsp56004/d, rev. 3 2-15 figure 2-11 dram page mode write cycle col. address row address col. address last column address 48 46 60 50 48 65 41 54 52 54 49 49 49 61 59 58 58 53 51 55 56 57 57 57 62 data out 69 68 68 67 73 67 data out data out mras mcas ma0Cma10 mwr mrd md0Cmd7 aa0265 70 66 68 67 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-16 dsp56004/d, rev. 3 motorola specifications external memory interface (emi) dram refresh timing external memory interface (emi) dram refresh timing (c l = 50 pf + 2 ttl loads) table 2-9 external memory interface (emi) dram refresh timing no. characteristics sym. timing mode exp. 50 mhz 66 mhz 81 mhz unit min max min max min max 81 ras deassertation to ras assertion t rp slow fast 6 t c C 7 4 t c C 7 113 73 84 54 67.1 42.4 ns ns 82 cas deassertation to cas assertion t cpn slow fast 5 t c C 7 3 t c C 7 93 53 71 38 54.7 30 ns ns 83 refresh cycle time t rc slow fast 12 t c 8 t c 240 160 181.8 121.2 148.2 98.8 ns ns 84 ras assertion pulse width t ras slow fast 6 t c C 9 4 t c C 9 111 71 81.9 51.6 65.1 40.4 ns ns 85 ras deassertation to ras assertion for refresh cycle 1 t rp slow fast 5 t c C 5 3 t c C 5 95 55 70 40 55.7 32 ns ns 86 cas assertion to ras assertion on refresh cycle t csr t c C 7 13 8 5.3 ns 87 ras assertion to cas deassertation on refresh cycle t chr slow fast 6 t c C 15 4 t c C 15 105 65 75.9 45.6 59.1 34.4 ns ns 88 ras deassertation to cas assertion on a refresh cycle t rpc slow fast 5 t c C 11 3 t c C 11 89 49 65 34 50.7 26 ns ns 89 cas deassertation to data not valid t off 0 00 0 ns note: 1. this happens when a refresh cycle is followed by an access cycle. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications external memory interface (emi) sram timing motorola dsp56004/d, rev. 3 2-17 external memory interface (emi) sram timing (c l = 50 pf + 2 ttl loads) figure 2-12 cas before ras refresh cycle table 2-10 external memory interface (emi) sram timing no. characteristics symbol expression 50 mhz 66 mhz 81 mhz unit min max min max min max 91 address valid and cs assertion pulse width t rc , t wc 4 t c C 11 + ws t c 69 50 38.4 ns 92 address valid to rd or wr assertion t as t c + t l C 13 17 10 5.5 ns 93 rd or wr assertion pulse width t wp 2 t c C 5 + ws t c 3523 20 ns 94 rd or wr deassertation to rd or wr assertion 2 t c C 11 29 19 13.7 ns 95 rd or wr deassertation to address not valid t wr t h C 6 420.2 ns 96 address valid to input data valid t aa , t ac 3 t c + t l C15 + ws t c 55 38 28.2 ns 97 rd assertion to input data valid t oe 2 t c C 15 + ws t c 2515 9.7 ns mras mcas data in md0Cmd7 83 81 84 85 88 82 87 89 86 aa0266 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-18 dsp56004/d, rev. 3 motorola specifications external memory interface (emi) sram timing 98 rd deassertation to data not valid (data hold time) t ohz 0 00 0 ns 99 address valid to wr deassertation t cw , t aw 3 t c + t l C14 + ws t c 56 39 29.2 ns 100 data setup time to wr deassertation t ds (t dw )t c + t l C 5 + ws t c 25 18 11.0 ns 101 data hold time from wr deassertation t dh t h C 6 420.2 ns 102 wr assertion to data valid t h + 4 14 12 10.2 ns 103 wr deassertation to data high impedance 1 t h + 10 20 18 16.2 ns 104 wr assertion to data active t h C 6 420.2 ns note: 1. this value is periodically sampled and not 100% tested. figure 2-13 sram read cycle table 2-10 external memory interface (emi) sram timing no. characteristics symbol expression 50 mhz 66 mhz 81 mhz unit min max min max min max ma0Cma14 ma15/ mcs3 ma16/ mcs2 / mcas ma17/ mcs1 / mras mcs0 rd wr data in md0Cmd7 91 92 94 93 95 94 98 97 96 aa0267 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications external memory interface (emi) sram timing motorola dsp56004/d, rev. 3 2-19 figure 2-14 sram write cycle ma0Cma14 ma15/ mcs3 ma16/ mcs2 / mcas ma17/ mcs1 / mras mcs0 wr rd data out md0Cmd7 91 92 94 93 95 94 103 100 aa0268 99 102 104 101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-20 dsp56004/d, rev. 3 motorola specifications serial audio interface (sai) timing serial audio interface (sai) timing (c l = 50 pf + 2 ttl loads) table 2-11 serial audio interface (sai) timing no. characteristics mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max 111 minimum serial clock cycle = t saicc (min) master slave 4 t c 3 t c + 5 80 65 61 51 49.4 42 ns ns 112 serial clock high period master slave 0.5 t saicc C 8 0.35 t saicc 32 23 22 18 16.7 14.7 ns ns 113 serial clock low period master slave 0.5 t saicc C 8 0.35 t saicc 32 23 22 18 16.7 14.7 ns ns 114 serial clock rise/fall time master slave 8 0.15 t saicc 8 10 8 8 8 6.3 ns ns 115 data in valid to sckr edge (data in set-up time) master slave 26 4 26 4 26 4 26 4 ns ns 116 sckr edge to data in not valid (data in hold time) master slave 0 14 0 14 0 14 0 14 ns ns 117 sckr edge to word select out valid (wsr out delay time) master 20 20 20 20 ns 118 word select in valid to sckr edge (wsr in set-up time) slave 12 12 12 12 ns 119 sckr edge to word select in not valid (wsr in hold time) slave 12 12 12 12 ns 121 sckt edge to data out valid (data out delay time) master slave 1 slave 2 13 40 t h + 34 13 40 44 13 40 41 13 40 40.2 ns ns ns 122 sckt edge to word select out valid (wst out delay time) master 19 19 19 19 ns 123 word select in valid to sckt edge (wst in set-up time) slave 12 12 12 12 ns 124 sckt edge to word select in not valid (wst in hold time) slave 12 12 12 12 ns note: 1. when the frequency ratio between parallel and serial clocks is 1:4 or greater 2. when the frequency ratio between parallel and serial clocks is 1:3 C 1:4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial audio interface (sai) timing motorola dsp56004/d, rev. 3 2-21 figure 2-15 sai receiver timing sckr (rckp = 1) sckr (rckp = 0) valid valid wsr (output) wsr (input) sdi0Csdi1 (data input) 111 112 113 111 113 114 114 112 116 115 118 119 117 aa0269 114 114 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-22 dsp56004/d, rev. 3 motorola specifications serial audio interface (sai) timing figure 2-16 sai transmitter timing valid 111 112 113 111 113 114 114 112 121 123 124 122 aa0270 114 114 sckt (tckp = 1) sckt (tckp = 0) wst (output) wst (input) sdo0Csdo2 (data output) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial host interface (shi) spi protocol timing motorola dsp56004/d, rev. 3 2-23 serial host interface (shi) spi protocol timing (c l = 50 pf; v ihs = 0.7 v cc , v ils = 0.3 v cc ) table 2-12 serial host interface (shi) spi protocol timing no. characteristics mode filter mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max tolerable spike width on clock or data in bypassed narrow wide 0 20 100 0 20 100 0 20 100 ns ns ns 141 minimum serial clock cycle = t spicc (min) for frequency below 33 mhz 1 for frequency above 33 mhz 1 cpha = 0, cpha = 1 2 cpha = 1 master slave slave bypassed bypassed narrow wide bypassed narrow wide bypassed narrow wide 4 t c 6 t c 1000 2000 3 t c 3 t c + 25 3 t c + 85 3 t c + 79 3 t c + 431 3 t c + 1022 120 1000 2000 60 85 145 139 491 1082 91 1000 2000 45 70 130 124 476 1067 74.1 1000 2000 37 62 122 116 468 1059 ns ns ns ns ns ns ns ns ns ns 142 serial clock high period cpha = 0, cpha = 1 2 cpha = 1 master slave slave bypassed narrow wide bypassed narrow wide 0.5 t spicc C10 t c + 8 t c + 31 t c + 43 t c + t h + 40 t c + t h + 216 t c + t h + 511 50 28 51 63 70 246 541 35 23 46 58 63 239 534 27.0 20.3 43.3 55.3 58.5 235 530 ns ns ns ns ns ns ns 143 serial clock low period cpha = 0, cpha = 1 2 cpha = 1 master slave slave bypassed narrow wide bypassed narrow wide 0.5 t spicc C10 t c + 8 t c + 31 t c + 43 t c + t h + 40 t c + t h + 216 t c + t h + 511 50 28 51 63 70 246 541 35 23 46 58 63 239 534 27.0 20.3 43.3 55.3 58.5 235 550 ns ns ns ns ns ns ns 144 serial clock rise/fall time master slave 10 2000 10 2000 10 2000 10 2000 ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-24 dsp56004/d, rev. 3 motorola specifications serial host interface (shi) spi protocol timing 146 ss assertion to first sck edge cpha = 0 cpha = 1 slave slave bypassed narrow wide bypassed narrow wide t c + t h + 35 t c + t h + 35 t c + t h + 35 6 0 0 65 65 65 6 0 0 58 58 58 6 0 0 53.5 53.5 53.5 6 0 0 ns ns ns ns ns ns 147 last sck edge to ss not asserted cpha = 0 cpha = 1 3 slave slave bypassed narrow wide bypassed narrow wide t c + 6 t c + 70 t c + 197 2 66 193 26 90 217 2 66 193 21 85 212 2 66 193 18.3 82.4 209 2 66 193 ns ns ns ns ns ns 148 data in valid to sck edge (data in set-up time) master slave bypassed narrow wide bypassed narrow wide 0 max {(37 C t c ), 0} max {(52 C t c ), 0} 0 max {(38 C t c ), 0} max {(53 C t c ), 0} 0 17 32 0 18 33 0 22 37 0 23 38 0 25 40 0 26 41 ns ns ns ns ns ns 149 sck edge to data in not valid (data in hold time) master slave bypassed narrow wide bypassed narrow wide 2 t c + 17 2 t c + 18 2 t c + 28 2 t c + 17 2 t c + 18 2 t c + 28 57 58 68 57 58 68 47 48 58 47 48 58 41.7 42.7 52.7 41.7 42.7 52.7 ns ns ns ns ns ns 150 ss assertion to data out active slave 4 44 4 ns 151 ss deassertation to data high impedance 4 slave 24 24 24 24 ns 152 sck edge to data out valid (data out delay time) cpha = 0, cpha = 1 2 cpha = 1 master slave slave bypassed narrow wide bypassed narrow wide bypassed narrow wide 41 214 504 41 214 504 t c + t h + 40 t c + t h + 216 t c + t h + 511 41 214 504 41 214 504 70 246 541 41 214 504 41 214 504 63 239 534 41 214 504 41 214 504 58.5 235 530 ns ns ns ns ns ns ns ns ns table 2-12 serial host interface (shi) spi protocol timing (continued) no. characteristics mode filter mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial host interface (shi) spi protocol timing motorola dsp56004/d, rev. 3 2-25 153 sck edge to data out not valid (data out hold time) master slave bypassed narrow wide bypassed narrow wide 0 57 163 0 57 163 0 57 163 0 57 163 0 57 163 0 57 163 0 57 163 0 57 163 ns ns ns ns ns ns 154 ss assertion to data out valid cpha = 0 slave t c + t h + 35 65 58 53.5 ns 157 first sck sampling edge to hreq output deassertation slave bypassed narrow wide 3 t c + t h + 32 3 t c + t h + 209 3 t c + t h + 507 102 279 577 85 262 560 75 252 550 ns ns ns 158 last sck sampling edge to hreq output not deasserted cpha = 1 slave bypassed narrow wide 2 t c + t h + 6 2 t c + t h + 63 2 t c + t h + 169 56 113 219 44 101 207 36.9 93.9 200 ns ns ns 159 ss deassertation to hreq output not deasserted cpha = 0 slave 2 t c + t h + 7 57 45 37.9 ns 160 ss deassertation pulse width cpha = 0 slave t c + 4 24 19 16.3 ns 161 hreq in assertion to first sck edge master 0.5 t spicc + 2 t c + 6 106 82 67.7 ns 162 hreq in deassertation to last sck sampling edge (hreq in set-up time) cpha = 1 master 0 00 0 ns table 2-12 serial host interface (shi) spi protocol timing (continued) no. characteristics mode filter mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-26 dsp56004/d, rev. 3 motorola specifications serial host interface (shi) spi protocol timing 163 first sck edge to hreq in not asserted (hreq in hold time) master 0 00 0 ns note: 1. for an internal clock frequency below 33 mhz, the minimum permissible internal clock to serial clock frequency ratio is 4:1. for an internal clock frequency above 33 mhz, the minimum permissible internal clock to serial clock frequency ratio is 6:1. 2. in cpha = 1 mode, the spi slave supports data transfers at t spicc = 3 t c , if the user assures that the htx is written at least t c ns before the first edge of sck of each word.in cpha = 1 mode, the spi slave supports data transfers at t spicc = 3 t c , if the user assures that the htx is written at least t c ns before the first edge of sck of each word. 3. when cpha = 1, the ss line may remain active low between successive transfers. 4. periodically sampled, not 100% tested figure 2-17 spi master timing (cpha = 0) table 2-12 serial host interface (shi) spi protocol timing (continued) no. characteristics mode filter mode expression 50 mhz 66 mhz 81 mhz unit min max min max min max ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 149 149 148 152 153 163 161 aa0271 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial host interface (shi) spi protocol timing motorola dsp56004/d, rev. 3 2-27 figure 2-18 spi master timing (cpha = 1) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 148 149 152 153 163 161 aa0272 162 149 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-28 dsp56004/d, rev. 3 motorola specifications serial host interface (shi) spi protocol timing figure 2-19 spi slave timing (cpha = 0) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 141 144 144 143 142 154 150 152 153 148 149 159 157 aa0273 153 151 valid valid 148 149 147 160 146 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial host interface (shi) spi protocol timing motorola dsp56004/d, rev. 3 2-29 figure 2-20 spi slave timing (cpha = 1) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 144 144 143 142 150 152 148 149 158 aa0274 153 151 valid valid 148 147 146 152 149 157 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-30 dsp56004/d, rev. 3 motorola specifications serial host interface (shi) i 2 c protocol timing serial host interface (shi) i 2 c protocol timing (v ihs = 0.7 v cc , v ils = 0.3 v cc ) (v ohs = 0.8 v cc , v ols = 0.2 v cc ) (r p (min) = 1.5 k w ) table 2-13 shi i 2 c protocol timing standard i 2 c (c l = 400 pf, r p = 2 k w , 100 khz) no. characteristics symbol all frequencies unit min max tolerable spike width on scl or sda filters bypassed narrow filters enabled wide filters enabled 0 20 100 ns ns ns 171 minimum scl serial clock cycle t scl 10.0 m s 172 bus free time t buf 4.7 m s 173 start condition set-up time t su;sta 4.7 m s 174 start condition hold time t hd;sta 4.0 m s 175 scl low period t low 4.7 m s 176 scl high period t high 4.0 m s 177 scl and sda rise time t r 1.0 m s 178 scl and sda fall time t f 0.3 m s 179 data set-up time t su;dat 250 ns 180 data hold time t hd;dat 0.0 ns 182 scl low to data out valid t vd;dat 3.4 m s 183 stop condition set-up time t su;sto 4.0 m s note: refer to the dsp56004 users manual for a detailed description of how to use the different filtering modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial host interface (shi) i 2 c protocol timing motorola dsp56004/d, rev. 3 2-31 the programmed serial clock cycle, t i 2 ccp , is specified by the value of the hdm5C hdm0 and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is: where ? hrs is the prescaler rate select bit. when hrs is cleared, the fixed divide-by- eight prescaler is operational. when hrs is set, the prescaler is bypassed. ? hdm5Chdm0 are the divider modulus select bits. ? a divide ratio from 1 to 64 (hdm5Chdm0 = 0 to $3f) may be selected. in i 2 c mode, you may select a value for the programmed serial clock cycle from 6 t c (hdm5Chdm0 = 2, hrs = 1) to 1024 t c (hdm5Chdm0 = $3f, hrs = 0). the dsp56004 provides an improved i 2 c bus protocol. in addition to supporting the 100 khz i 2 c bus protocol, the shi in i 2 c mode supports data transfers at up to 1000 khz. the actual maximum frequency is limited by the bus capacitances (c l ),the pull- up resistors (r p ), (which affect the rise and fall time of sda and scl, (see table below)), and by the input filters. consideration for programming the shi clock control register (hckr) C clock divide ratio: the master must generate a bus free time greater than t172 slave when operating with a dsp56004 shi i 2 c slave. the table below describes a few examples : table 2-14 considerations for programming the shi clock control register (hckr) conditions to be considered resulting limitations bus load master oper- ating freq. slave oper- ating freq. master filter mode slave filter mode t172 slave min. perm- issible t i 2 ccp t172 master maximum i 2 c serial frequency c l = 50 pf, r p = 2 k w 81 mhz 81 mhz bypassed narrow wide bypassed narrow wide 36 ns 60 ns 95 ns 52 t c 56 t c 62 t c 41 ns 66 ns 103 ns 1010 khz 825 khz 634 khz t i 2 ccp tc 2 hdm[5:0] 1 + () 7 1 hrs C () 1 + () [] = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-32 dsp56004/d, rev. 3 motorola specifications serial host interface (shi) i 2 c protocol timing example: for c l = 50 pf, r p = 2 k w , f = 88 mhz, bypassed filter mode: the master, when operating with a dsp56004 shi i 2 c slave with an 88 mhz operating frequency, must generate a bus free time greater than 36 ns (t172 slave). thus, the minimum permissible t i 2 ccp is 56 t c which gives a bus free time of at least 41 ns (t172 master). this implies a maximum i 2 c serial frequency of 1010 khz. in general, bus performance may be calculated from the c l and r p of the bus, the input filter modes and operating frequencies of the master and the slave. table 2-15 contains the expressions required to calculate all relevant performance timing for a given c l and r p . table 2-15 shi improved i 2 c protocol timing improved i 2 c (c l = 50 pf, r p = 2 k w ) no. char. sym. mode filter mode expression 50 mhz 2 66 mhz 3 81 mhz 4 u n i t min max min max min max tolerable spike width on scl or sda bypassed narrow wide 0 20 100 0 20 100 0 20 100 0 20 100 ns ns ns 171 scl serial clock cycle t scl master slave bypassed narrow wide bypassed narrow wide t i 2 ccp + 3 t c +72 +t r t i 2 ccp + 3 t c + 245 + t r t i 2 ccp + 3 t c + 535 + t r 4 t c + t h + 172 + t r 4 t c + t h + 366 + t r 4 t c + t h + 648 + t r 1050 1263 1593 500 694 976 1007 1225 1591 478 672 954 989 1212 1576 466 660 942 ns ns ns ns ns ns 172 bus free time t buf master slave bypassed narrow wide bypassed narrow wide 0.5 t i 2 ccp C 42 C t r 0.5 t i 2 ccp C 42 C t r 0.5 t i 2 ccp C 42 C t r 2 t c + 11 2 t c + 35 2 t c + 70 60 80 100 51 75 110 46 68 102 41 65 100 41.1 65.8 103 35.7 59.7 94.7 ns ns ns ns ns ns 173 start condition set-up time t su;sta slave bypassed narrow wide 12 50 150 12 50 150 12 50 150 12 50 150 ns ns ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial host interface (shi) i 2 c protocol timing motorola dsp56004/d, rev. 3 2-33 174 start condition hold time t hd;sta master slave bypassed narrow wide bypassed narrow wide 0.5 t i 2 ccp + 12 C t f 0.5 t i 2 ccp + 12 C t f 0.5 t i 2 ccp + 12 C t f 2 t c + t h + 21 2 t c + t h + 100 2 t c + t h + 200 332 352 372 71 150 250 318 340 378 59 138 238 313 338 375 51.9 131 231 ns ns ns ns ns ns 175 scl low period t low master slave bypassed narrow wide bypassed narrow wide 0.5 t i 2 ccp + 18 C t f 0.5 t i 2 ccp + 18 C t f 0.5 t i 2 ccp + 18 C t f 2 t c + 74 + t r 2 t c + 286 + t r 2 t c + 586 + t r 338 358 378 352 564 864 324 346 384 342 554 854 319 344 381 337 536 849 ns ns ns ns ns ns 176 scl high period t high master slave bypassed narrow wide bypassed narrow wide 0.5 t i 2 ccp + 2 t c + 19 0.5 t i 2 ccp + 2 t c + 144 0.5 t i 2 ccp + 2 t c + 356 2 t c + t h C 1 2 t c + t h + 18 2 t c + t h + 30 379 544 776 49 68 80 375 523 773 37 56 68 365 514 763 30 49 61 ns ns ns ns ns ns 177 scl rise time output 1 input t r 1.7 r p (c l + 20) 2000 238 2000 238 2000 238 2000 ns ns 178 scl fall time output 1 input t f 20 + 0.1 (c l C 50) 2000 20 2000 20 2000 20 2000 ns ns 179 data set-up time t su;dat bypassed narrow wide t c + 8 t c + 60 t c + 74 28 80 94 23 75 89 20 72 86 ns ns ns table 2-15 shi improved i 2 c protocol timing (continued) improved i 2 c (c l = 50 pf, r p = 2 k w ) no. char. sym. mode filter mode expression 50 mhz 2 66 mhz 3 81 mhz 4 u n i t min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-34 dsp56004/d, rev. 3 motorola specifications serial host interface (shi) i 2 c protocol timing 180 data hold time t hd;dat bypassed narrow wide 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns 182 scl low to data out valid t vd;dat bypassed narrow wide 2 t c + 71 + t r 2 t c + 244 + t r 2 t c + 535 + t r 349 522 813 339 512 803 344 507 798 ns ns ns 183 stop condition set-up time t su;sto master slave bypassed narrow wide bypassed narrow wide 0.5 t i 2 ccp + t c + t h + 11 0.5 t i 2 ccp + t c + t h + 69 0.5 t i 2 ccp + t c + t h + 183 11 50 150 381 459 613 11 50 150 359 440 592 11 50 150 351 433 584 11 50 150 ns ns ns ns ns ns 184 hreq in deassertation to last scl edge (hreq in set-up time) master bypassed narrow wide 0 0 0 0 0 0 0 0 0 0 0 0 ns ns ns 186 first scl sampling edge to hreq output deassertation slave bypassed narrow wide 3 t c + t h + 32 3 t c + t h + 209 3 t c + t h + 507 102 279 577 85 262 560 75 252 550 ns ns ns 187 last scl edge to hreq output not deasserted slave bypassed narrow wide 2 t c + t h + 6 2 t c + t h + 63 2 t c + t h + 169 56 113 219 44 101 207 37 93.9 200 ns ns ns 188 hreq in assertion to first scl edge master bypassed narrow wide t i 2 ccp + 2 t c + 6 t i 2 ccp + 2 t c + 6 t i 2 ccp + 2 t c + 6 726 766 846 688 733 809 673 722 796 ns ns ns table 2-15 shi improved i 2 c protocol timing (continued) improved i 2 c (c l = 50 pf, r p = 2 k w ) no. char. sym. mode filter mode expression 50 mhz 2 66 mhz 3 81 mhz 4 u n i t min max min max min max f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications serial host interface (shi) i 2 c protocol timing motorola dsp56004/d, rev. 3 2-35 189 first scl edge to hreq in not asserted (hreq in hold time) master 0 000ns note: 1. c l is in pf, r p is in k w , and result is in ns. 2. a t i 2 ccp of 34 t c (the maximum permitted for the given bus load) was used for the calculations in the bypassed filter mode. a t i 2 ccp of 36 t c (the maximum permitted for the given bus load) was used for the calculations in the narrow filter mode. a t i 2 ccp of 40 t c (the maximum permitted for the given bus load) was used for the calculations in the wide filter mode. 3. a t i 2 ccp of 43 t c (the maximum permitted for the given bus load) was used for the calculations in the bypassed filter mode. a t i 2 ccp of 46 t c (the maximum permitted for the given bus load) was used for the calculations in the narrow filter mode. a t i 2 ccp of 51 t c (the maximum permitted for the given bus load) was used for the calculations in the wide filter mode. 4. a t i 2 ccp of 52 t c (the maximum permitted for the given bus load) was used for the calculations in the bypassed filter mode. a t i 2 ccp of 56 t c (the maximum permitted for the given bus load) was used for the calculations in the narrow filter mode. a t i 2 ccp of 62 t c (the maximum permitted for the given bus load) was used for the calculations in the wide filter mode. 5. refer to the dsp56004 users manual for a detailed description of how to use the filtering modes. figure 2-21 i 2 c timing table 2-15 shi improved i 2 c protocol timing (continued) improved i 2 c (c l = 50 pf, r p = 2 k w ) no. char. sym. mode filter mode expression 50 mhz 2 66 mhz 3 81 mhz 4 u n i t min max min max min max start scl hreq sda ack msb lsb stop 171 stop 173 176 175 177 178 180 179 172 186 182 183 189 174 188 184 187 aa0275 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-36 dsp56004/d, rev. 3 motorola specifications general purpose i/o (gpio) timing general purpose i/o (gpio) timing (c l = 50 pf + 2 ttl loads) table 2-16 gpio timing no. characteristics expression all frequencies unit min max 201 extal edge to gpio out valid (gpio out delay time) 26 26 ns 202 extal edge to gpio out not valid (gpio out hold time) 22ns 203 gpio in valid to extal edge (gpio in set-up time) 10 10 ns 204 extal edge to gpio in not valid (gpio in hold time) 6 6 ns figure 2-22 gpio timing valid (input) gpio0C (output) extal (input) (note 1) note: 1. valid when the ratio between extal frequency and internal clock frequency equals 1 201 202 204 203 aa0276 gpio3 gpio0C gpio3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications on-chip emulation (once ? ) timing motorola dsp56004/d, rev. 3 2-37 on-chip emulation (once ? ) timing (c l = 50 pf + 2 ttl loads) table 2-17 once timing no. characteristics all frequencies unit min max 230 dsck low 40 ns 231 dsck high 40 ns 232 dsck cycle time 200 ns 233 dr asserted to dso (ack ) asserted 5 t c ns 234 dsck high to dso valid 42 ns 235 dsck high to dso invalid 3 ns 236 dsi valid to dsck low (set-up) 15 ns 237 dsck low to dsi invalid (hold) 3 ns 238 last dsck low to os0Cos1, ack active 3 t c + t l ns 239 dso (ack ) asserted to first dsck high 2 t c ns 240 dso (ack ) assertion width 4 t c + t h C 3 5 t c + 7 ns 241 dso (ack ) asserted to os0Cos1 high impedance 1 0ns 242 os0Cos1 valid to extal transition #2 t c C 21 ns 243 extal transition #2 to os0Cos1 invalid 0 ns 244 last dsck low of read register to first dsck high of next command 7 t c + 10 ns 245 last dsck low to dso invalid (hold) 3 ns 246 dr assertion to extal transition #2 for wake up from wait state 10 t c C 10 ns 247 extal transition #2 to dso after wake up from wait state 17 t c ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-38 dsp56004/d, rev. 3 motorola specifications on-chip emulation (once ? ) timing 248 dr assertion width ? to recover from wait ? to recover from wait and enter debug mode 15 13 t c + 15 12 t c C 15 ns ns 249 dr assertion to dso (ack ) valid (enter debug mode) after asynchronous recovery from wait state 17 t c ns 250a dr assertion width to recover from stop 2 ? stable external clock, omr bit 6 = 0 ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17 = 1 15 15 15 65548 t c + t l 20 t c + t l 13 t c + t l ns ns ns 250b dr assertion width to recover from stop and enter debug mode 2 ? stable external clock, omr bit 6 = 0 ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17 = 1 65549 t c + t l 21 t c + t l 14 t c + t l ns ns ns 251 dr assertion to dso (ack ) valid (enter debug mode) after recovery from stop state 2 ? stable external clock, omr bit 6 = 0 ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17 = 1 65553 t c + t l 25 t c + t l 18 t c + t l ns ns ns note: 1. maximum t l 2. periodically sampled, not 100% tested figure 2-23 dsp56004 once serial clock timing table 2-17 once timing (continued) no. characteristics all frequencies unit min max dsck (input) 246 246 231 232 230 aa0277 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications on-chip emulation (once ? ) timing motorola dsp56004/d, rev. 3 2-39 figure 2-24 dsp56004 once acknowledge timing figure 2-25 dsp56004 once data i/o to status timing figure 2-26 dsp56004 once read timing figure 2-27 dsp56004 once data i/o status timing dr (input) dso (output) ack 233 240 aa0278 dsck (input) dso (output) ( ack ) (os1) dsi (input) (os0) (note 1) note: 1. high impedance, external pull-down resistor (last) 236 237 238 aa0279 dsck (input) dso (output) (os0) (note 1) note: 1. high impedance, external pull-down resistor (last) 235 245 aa0280 234 note: 1. high impedance, external pull-down resistor os1 (output) dso (output) (dsck input) os0 (output) (note 1) (dso output) (dsi input) (note 1) 241 239 240 241 236 237 aa0281 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-40 dsp56004/d, rev. 3 motorola specifications on-chip emulation (once ? ) timing figure 2-28 dsp56004 once extal to status timing figure 2-29 dsp56004 once dsck next command after read register timing figure 2-30 synchronous recovery from wait state figure 2-31 asynchronous recovery from wait state extal os0Cos1 (output) note: 1. high impedance, external pull-down resistor 2. valid when the ratio between extal frequency and clock frequency equals 1 (note 1) (note 2) 242 243 aa0282 dsck (input) (next command) 244 aa0283 t0, t2 t1, t3 extal dr (input) dso (output) 248 246 247 aa0284 dr (input) dso (output) 248 249 aa0285 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications on-chip emulation (once ? ) timing motorola dsp56004/d, rev. 3 2-41 figure 2-32 asynchronous recovery from stop state dr (input) dso (output) 250 251 aa0286 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 2-42 dsp56004/d, rev. 3 motorola specifications on-chip emulation (once ? ) timing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004/d, rev. 3 3-1 section 3 packaging pin-out and package information this section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in section 1 are allocated. the dsp56004 is available in an 80-pin plastic quad flat pack (pqfp) package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-2 dsp56004/d, rev. 3 motorola packaging pin-out and package information pqfp package description top and bottom views of the pqfp package are shown in figure 3-1 and figure 3-2 with their pin-outs. figure 3-1 top view (top view) orientation mark 61 41 note: an overbar indicates the signal is asserted when the voltage = ground (active low). to simplify locating the pins, each fifth pin is shaded in the illustration. 21 1 dr md7 md6 md5 md4 gnd d md3 md2 md1 v ccd md0 gnd d gpio3 gpio2 gpio1 gpio0 mrd mwr ma17/mcs1 /mras ma16/mcs2 /mcas v ccs modc/nmi modb/irqb moda/irqa reset miso/sda gnd s v ccp pcap gnd p pinit gnd q v ccq extal sck/scl ma0 ma1 ma2 ma3 gnd a dsck/os1 dsi/os0 dso sdi0 sdi1 wsr gnd s v ccq gnd q sckr wst sckt v ccs sdo0 sdo1 sdo2 gnd s hreq ss /ha2 mosi/ha0 gnd a mcs0 ma15/mcs3 ma14 ma13 v cca ma12 gnd a v ccq gnd q ma11 ma10 ma9 ma8 gnd a ma7 v cca ma6 ma5 ma4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pin-out and package information motorola dsp56004/d, rev. 3 3-3 figure 3-2 bottom view (bottom view) orientation mark 61 41 note: an overbar indicates the signal is asserted when the voltage = ground (active low). to simplify locating the pins, each fifth pin is shaded in the illustration. 21 1 v ccs modc/nmi modb/irqb moda/irqa reset miso/sda gnd s v ccp pcap gndp pinit gnd q v ccq extal sck/scl ma0 ma1 ma2 ma3 gnd a dr md7 md6 md5 md4 gnd d md3 md2 md1 v ccd md0 gnd d gpio3 gpio2 gpio1 gpio0 mrd mwr ma17/mcs1 /mras ma16/mcs2 /mcas gnd a mcs0 ma15/mcs3 ma14 ma13 v cca ma12 gnd a v ccq gnd q ma11 ma10 ma9 ma8 gnd a ma7 v cca ma6 ma5 ma4 dsck/os1 dsi/os0 dso sdi0 sdi1 wsr gnd s v ccq gnd q sckr wst sckt v ccs sdo0 sdo1 sdo2 gnd s hreq ss /ha2 mosi/ha0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-4 dsp56004/d, rev. 3 motorola packaging pin-out and package information table 3-1 dsp56004 pin identification by pin number pin # signal name pin # signal name pin # signal name 1 gnd a 28 v ccq 55 wsr 2 mcs0 29 gnd q 56 sdi1 3 ma15/mcs3 30 pinit 57 sdi0 4 ma14 31 gnd p 58 dso 5 ma13 32 pcap 59 dsi/os0 6v cca 33 v ccp 60 dsck/os1 7 ma12 34 gnd s 61 dr 8 gnd a 35 miso/sda 62 md7 9v ccq 36 reset 63 md6 10 gnd q 37 moda/irqa 64 md5 11 ma11 38 modb/irqb 65 md4 12 ma10 39 modc/nmi 66 gnd d 13 ma9 40 v ccs 67 md3 14 ma8 41 mosi/ha0 68 md2 15 gnd a 42 ss /ha2 69 md1 16 ma7 43 hreq 70 v ccd 17 v cca 44 gnd s 71 md0 18 ma6 45 sdo2 72 gnd d 19 ma5 46 sdo1 73 gpio3 20 ma4 47 sdo0 74 gpio2 21 gnd a 48 v ccs 75 gpio1 22 ma3 49 sckt 76 gpio0 23 ma2 50 wst 77 mrd 24 ma1 51 sckr 78 mwr 25 ma0 52 gnd q 79 ma17/mcs1 / mras 26 sck/scl 53 v ccq 80 ma16/mcs2 / mcas 27 extal 54 gnd s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pin-out and package information motorola dsp56004/d, rev. 3 3-5 table 3-2 dsp56004 pin identification by signal name signal name pin # signal name pin # signal name pin # dr 61 ma5 19 mrd 77 dsck 60 ma6 18 mwr 78 dsi 59 ma7 16 nmi 39 dso 58 ma8 14 os0 59 extal 27 ma9 13 os1 60 gnd a 1 ma10 12 pcap 32 gnd a 8 ma11 11 pinit 30 gnd a 15 ma12 7 reset 36 gnd a 21 ma13 5 sck 26 gnd d 66 ma14 4 sckr 51 gnd d 72 ma15 3 sckt 49 gnd p 31 ma16 80 scl 26 gnd q 10 ma17 79 sda 35 gnd q 29 mcas 80 sdi0 57 gnd q 52 mcs0 2 sdi1 56 gnd s 34 mcs1 79 sdo0 47 gnd s 44 mcs2 80 sdo1 46 gnd s 54 mcs3 3 sdo2 45 gpio0 76 md0 71 ss 42 gpio1 75 md1 69 v cca 6 gpio2 74 md2 68 v cca 17 gpio3 73 md3 67 v ccd 70 ha0 41 md4 65 v ccp 33 ha2 42 md5 64 v ccq 9 hreq 43 md6 63 v ccq 28 irqa 37 md7 62 v ccq 53 irqb 38 miso 35 v ccs 40 ma0 25 moda 37 v ccs 48 ma1 24 modb 38 wsr 55 ma2 23 modc 39 wst 50 ma3 22 mosi 41 ma4 20 mras 79 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-6 dsp56004/d, rev. 3 motorola packaging pin-out and package information table 3-3 dsp56004 power supply pins pin # signal name circuit supplied 6v cca address bus buffers 17 1 gnd a 8 15 21 70 v ccd data bus buffers 66 gnd d 72 9v ccq internal logic 28 53 10 gnd q 29 52 33 v ccp pll 31 gnd p 40 v ccs serial ports 48 34 gnd s 44 54 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . packaging pin-out and package information motorola dsp56004/d, rev. 3 3-7 figure 3-3 80-pin plastic quad flat pack (pqfp) mechanical information l min max millimeters dim a b c d e f g h j k l m n p q r s t u v w x 13.90 13.90 2.15 0.22 2.00 0.22 - 0.13 0.65 55 0.13 05 0.13 16.95 0.13 05 16.95 0.35 14.10 14.10 2.45 0.38 2.40 0.33 0.25 0.23 0.95 105 0.17 75 0.30 17.45 - - 17.45 0.45 0.65 bsc 12.35 bsc 0.325 bsc 1.6 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. p -a,b,d- b b detail a f d n section b-b j c 0.20 a-b d s s m -h- datum plane detail c k q r t w x u 0.01 -h- datum plane detail c h seating plane -c- c m g e 60 61 80 120 21 40 41 -d- -b- -a- b a l s v detail a h 0.20 a-b d s s m c 0.20 a-b d a-b 0.05 s s m 0.20 c a-b d 0.05 a-b s s 0.20 h a-b d mss m m case 841b-01 issue o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 3-8 dsp56004/d, rev. 3 motorola packaging ordering drawings ordering drawings complete mechanical information regarding dsp56004 packaging is available by facsimile through motorola's mfax? system. call the following number to obtain information by facsimile: the mfax automated system requests the following information: ? the receiving facsimile telephone number including area code or country code ? the callers personal identification number (pin) note: for first time callers, the system provides instructions for setting up a pin, which requires entry of a name and telephone number. ? the type of information requested: C instructions for using the system C a literature order form C specific part technical information or data sheets C other information described by the system messages a total of three documents may be ordered per call. the dsp56004 80-pin pqfp package mechanical drawing is referenced as 841b-01. (602) 244-6591 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004/d, rev. 3 4-1 section 4 design considerations thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature ?c r q ja = package junction-to-ambient thermal resistance ?c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r q ja = package junction-to-ambient thermal resistance ?c/w r q jc = package junction-to-case thermal resistance ?c/w r q ca = package case-to-ambient thermal resistance ?c/w r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. this model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. t j t a p d r q ja () + = r q ja r q jc r q ca + = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-2 dsp56004/d, rev. 3 motorola design considerations thermal design considerations the thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. again, if the estimations obtained from r q ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: ? to minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. ? to define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. ? if the temperature of the package case (t t ) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (t j C t t )/p d . as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. hence, the new thermal metric, thermal characterization parameter or y jt , has been defined to be (t j C t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . design considerations electrical design considerations motorola dsp56004/d, rev. 3 4-3 electrical design considerations use the following list of recommendations to assure correct dsp operation: ? provide a low-impedance path from the board power supply to each v cc pin on the dsp, and from the board ground to each gnd pin. ? use at least four 0.01C0.1 m f bypass capacitors positioned as close as possible to the four sides of the package to connect the v cc power source to gnd. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v cc and gnd pins are less than 0.5 in per capacitor lead. ? use at least a four-layer printed circuit board (pcb) with two inner layers for v cc and gnd. ? because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. this recommendation particularly applies to the address and data buses as well as the irqa , irqb , and nmi pins. maximum printed circuit board (pcb) trace lengths on the order of 6 inches are recommended. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v cc and gnd circuits. ? all inputs must be terminated (i.e., not allowed to float) using cmos levels, except as noted in section 1 . ? take special care to minimize noise levels on the v ccp and gnd p pins. ? if multiple dsp56004 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-4 dsp56004/d, rev. 3 motorola design considerations power consumption considerations power consumption considerations power dissipation is a key issue in portable dsp applications. some of the factors which affect current consumption are described in this section. most of the current consumed by cmos devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. current consumption is described by the formula: equation 3: where: c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle the maximum internal current (i cci max) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. the typical internal current (i ccityp ) value reflects the average switching of the internal buses on typical operating conditions. for applications that require very low current consumption: ? minimize the number of pins that are switching. ? minimize the capacitive load on the pins. ? connect the unused inputs to pull-up or pull-down resistors. ? disable unused peripherals. ? disable unused pin activity. example 4-1 current consumption for an i/o pin loaded with 50 pf capacitance, operating at 5.5 v, and with a 81 mhz clock, toggling at its maximum possible rate (20 mhz), the current consumption is: equation 4: i cvf = i5010 12 C 5.5 20 10 6 5.5ma == f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . design considerations power consumption considerations motorola dsp56004/d, rev. 3 4-5 current consumption test code: org p:reset jmp main org p:main movep #$180000,x:$fffd move #0,r0 move #0,r4 move #$00ff,m0 move #$00ff,m4 nop rep #256 move r0,x:(r0)+ rep #256 mov r4,y:(r4)+ clr a move l:(r0)+,a rep #30 mac x0,y0,a x:(r0)+,x0 y:(r4)+,y0 move a,p:(r5) jmp tp1 tp1 nop jmp main f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4-6 dsp56004/d, rev. 3 motorola design considerations power-up considerations power-up considerations to power-up the device properly, ensure that the following conditions are met: ? stable power is applied to the device according to the specifications in table 2-3 (dc electrical characteristics). ? the external clock oscillator is active and stable. ? reset is asserted according to the specifications in table 2-7 (reset, stop, mode select, and interrupt timing). ? the following input pins are driven to valid voltage levels: dr , pinit, moda, modb, and modc. care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on table 2-1 (maximum ratings), at all phases of the power-up procedure. this may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip. at the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. this is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola dsp56004/d, rev. 3 5-1 section 5 ordering information consult a motorola semiconductor sales office or authorized distributor to determine product availability and to place an order. table 5-1 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56004 5 v quad flat pack (qfp) 80 50 dsp56004fj50 66 dsp56004fj66 81 dsp56004fj81 dsp56004rom 1 5 v quad flat pack (qfp) 80 50 customer specific 66 customer specific 81 customer specific note: 1. for additional information on future part development, or to request specific rom-based support, call your local motorola semiconductor sales office or authorized distributor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa/europe/locations not listed : motorola literature distribution p.o. box 5405 denver, colorado 80217 303-675-2140 1 (800) 441-2447 mfax? : rmfax0@email.sps.mot.com touchtone (602) 244-6609 us & canada only (800) 774-1848 asia/pacific : motorola semiconductors h.k. ltd. 8b tai ping industrial park 51 ting kok road tai po, n.t., hong kong 852-26629298 technical resource center: 1 (800) 521-6274 dsp helpline dsphelp@dsp.sps.mot.com japan : nippon motorola ltd. tatsumi-spd-jldc 6f seibu-butsuryu-center 3-14-2 tatsumi koto-ku tokyo 135, japan 81-3-3521-8315 internet : http://www.motorola-dsp.com once, mfax, and symphony are trademarks of motorola, inc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
Price & Availability of DSP56004UMAD
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |